B.S. Electrical and Electronics Engineering and M. Sc. Computer Science from Birla Institute of Technology and Science (India). M.S. and Ph.D. in Computer Science from the University of Wisconsin
Computer Architecture (with emphasis on micro architectures of general-purpose, high-performance microprocessors),Techniques to Achieve High Performance, Low Power, and Fault Tolerance, Speculative Threading Techniques for Simultaneously-Multithreaded Processors and Chip Multiprocessors.
Assurable Software and Architecture
Recent work on fault tolerance has built on previously published fault detection using SMT and provide recovery without much performance loss beyond detection. Participated in earliest work on leakage power reduction in caches in the low power project. In the Skipper work, helped devise techniques to perform out-of-order fetch to skip over difficult-to-predict branches transparently without any software modifications. Collaboration in the speculative multi-threading project explored the idea that certain speculative accesses, called idenpotent accesses, need not be buffered, can be directly placed in committed storage, and still not violate necessary and sufficient conditions for idempotency. Work on memory consistency models shows that with speculative buffering, Sequential Consistency (SC) can be made to emulate Release Consistency (RC), and SC can be made to achieve RC's performance.
Listed in the ISCA Hall of Fame.
ISCA 1995 paper “Multiscalar Processors” selected in “25 years of the International Symposium on Computer Architecture - Selected Papers”.
1999 NSF CAREER award
Voted HKN's "Turkey" Professor, 1999
A record of four ISCA papers in a single year (in 2003). Only two others in the history of ISCA.
ISCA 2003 paper "Transient-Fault Recovery for Chip Multiprocessors" and ISCA 2005 paper "Opportunistic transient-fault detection" selected as one of IEEE Micro's Top Ten papers "most relevant to industry and significant in contribution to the field of computer architecture" in those years.
First Prize in the 2009 Burton D. Morgan Business Plan Competition for the business plan on commercializing programmable lab-on-a-chip technology.
HKN Outstanding Professor ("for dedication to education"), Fall 2014.
Accelerating Private Key Cryptography via Multithreading on Symmetric Multiprocessors (with P. Dongara), Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), (March 2003)
I am interested in computer architecture with emphasis on microarchitectures of general-purpose, high-performance microprocessors. I investigate techniques to achieve high performance, low power, and fault tolerance. I also work on speculative threading techniques for simultaneously-multithreaded processors and chip multiprocessors. In the recent fault tolerance work with Prof. Irith Pomeranz, we build on previously-published fault detection using SMT and provide recovery without much performance loss beyond detection. In the low power project with Profs. Kaushik Roy and Babak Falsafi, we did one of the earliest work on leakage power reduction in caches (which are the biggest problem for leakage). Modern microprocessors routinely perform out-of-order execution. In the Skipper work, we have devised techniques to perform out-of-order fetch to skip over difficult-to-predict branches transparently without any software modifications. In the speculative multithreading project with Profs. Rudi Eigenmann and Babak Falsafi, we explore the idea that certain speculative accesses, called idempotent accesses, need not be buffered, can be directly placed in committed storage, and still not violate correctness. This idea reduces stalls due to filling up of "speculative buffer space". We prove the necessary and sufficient conditions for idempotency. In the work on memory consistency models with Prof. Babak Falsafi, we show that with speculative buffering, Sequential Consistency (SC) can be made to emulate Release Consistency (RC), and SC can be made to achieve RC's performance. This paper has been included in the "Readings in Computer Architecture".